Texas-instruments Digital Signal Processor SM320F2812-HT Instrukcja Użytkownika Pobierz pdf (Strona 119)

Lead

Active

Trail

DIN

d(XCOHL-XRDL)

d(XCOH-XA)

d(XCOH-XZCSL)

d(XCOHL-XRDH)

h(XD)XRD

d(XCOHL-XZCSH)

XCLKOUT=XTIMCLK

XCLKOUT= 1/2 XTIMCLK

XZCS0AND1

, XZCS2,

XZCS6AND7

XA[0:18]

XRD

XWE

XR/W

XD[0:15]

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an

alignment cycle before an access to meet this requirement.

B. During alignment cycles, all signals transitions to their inactive state.

C. For USEREADY = 0, the external XREADY input signal is ignored.

D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.

su(XD)XRD

a(A)

a(XRD)

XREADY

SM320F2812-HT

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SGUS062B– JUNE 2009– REVISED JUNE 2011

6.23 External Interface Read Timing

Table 6-34. External Memory Interface Read Switching Characteristics

(1)

PARAMETER MIN MAX UNIT

d(XCOH-XZCSL)

Delay time, XCLKOUT high to zone chip-select active low 1 ns

d(XCOHL-XZCSH)

Delay time, XCLKOUT high/low to zone chip-select inactive high –2 3 ns

d(XCOH-XA)

Delay time, XCLKOUT high to address valid 2 ns

d(XCOHL-XRDL)

Delay time, XCLKOUT high/low to XRD active low 1 ns

d(XCOHL-XRDH

Delay time, XCLKOUT high/low to XRD inactive high –2 1 ns

h(XA)XZCSH

Hold time, address valid after zone chip-select inactive high

(2)

h(XA)XRD

Hold time, address valid after XRD inactive high

(2)

(1) Not production tested.

(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

Table 6-35. External Memory Interface Read Timing Requirements

(1)

MIN MAX UNIT

a(A)

Access time, read data from address valid (LR + AR) – 14

(2)

a(XRD)

Access time, read data valid from XRD active low AR – 12

(2)

su(XD)XRD

Setup time, read data valid before XRD strobe inactive high 12 ns

h(XD)XRD

Hold time, read data valid after XRD inactive high 0 ns

(1) Not production tested.

(2) LR = Lead period, read access. AR = Active period, read access. See Table 6-25.

Figure 6-29. Example Read Access

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