Texas-instruments Digital Signal Processor SM320F2812-HT Instrukcja Użytkownika Pobierz pdf (Strona 105)

XCLKOUT

d(XCOH-EVASOCL)

EVASOC

w(EVASOCL)

XCLKOUT

d(XCOH-EVBSOCL)

EVBSOC

w(EVBSOCL)

SM320F2812-HT

www.ti.com

SGUS062B– JUNE 2009– REVISED JUNE 2011

Table 6-15. External ADC Start-of-Conversion – EVA – Switching Characteristics

(1) (2)

PARAMETER MIN MAX UNIT

d(XCOH-EVASOCL)

Delay time, XCLKOUT high to EVASOC low 1 × t

c(SCO)

cycle

tw(EVASOCL) Pulse duration, EVASOC low 32 × t

c(HCO)

(1) XCLKOUT = SYSCLKOUT

(2) Not production tested.

Figure 6-18. EVASOC Timing

Table 6-16. External ADC Start-of-Conversion – EVB – Switching Characteristics

(1) (2)

PARAMETER MIN MAX UNIT

d(XCOH-EVBSOCL)

Delay time, XCLKOUT high to EVBSOC low 1 × t

c(SCO)

cycle

w(EVBSOCL)

Pulse duration, EVBSOC low 32 × t

c(HCO)

(1) XCLKOUT = SYSCLKOUT

(2) Not production tested.

Figure 6-19. EVBSOC Timing

6.16.2 Interrupt Timing

Table 6-17. Interrupt Switching Characteristics

PARAMETER MIN MAX UNIT

Without input

qualifier

Delay time, PDPINTx low to PWM

d(PDP-PWM)HZ

high-impedance state

1 × t

c(SCO)

+ IQT +

With input qualifier

(1)

Without input

3 × t

c(SCO)

Delay time, CxTRIP/TxCTRIP signals low

qualifier

d(TRIP-PWM)HZ

(2)

to PWM high-impedance state

With input qualifier [2 × t

c(SCO)

] + IQT

(1)

Delay time, INT low/high to

d(INT)

(2)

qual

+ 12t

c(XCO)

interrupt-vector fetch

(1) Input Qualification Time (IQT) = [5 × QUALPRD × 2] × t

c(SCO)

(2) Not production tested.

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