Texas-instruments Digital Signal Processor SM320F2812-HT Instrukcja Użytkownika Pobierz pdf (Strona 116)

SM320F2812-HT

SGUS062B–JUNE 2009 – REVISED JUNE 2011

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2. Active: AR ≥ 2 × t

c(XTIM)

AW ≥ 2 × t

c(XTIM)

NOTE

Restriction does not include external hardware wait states

3. Lead + Active: LR + AR ≥ 4 × t

c(XTIM)

LW + AW ≥ 4 × t

c(XTIM)

NOTE

Restriction does not include external hardware wait states

These requirements result in the following XTIMING register configuration restrictions:

Table 6-30. XTIMING Register Configuration Restrictions

(1) (2)

XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING

≥ 1 ≥ 2 0 ≥ 1 ≥ 2 0 0, 1

(1) Not production tested.

(2) No hardware to detect illegal XTIMING configurations

Table 6-31. XTIMING Register Configuration Restrictions

(1) (2)

XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING

≥ 2 ≥ 1 0 ≥ 2 ≥ 1 0 0, 1

(1) Not production tested.

(2) No hardware to detect illegal XTIMING configurations

Examples of valid and invalid timing when using Asynchronous XREADY:

Table 6-32. Asynchronous XREADY

(1) (2)

XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING

Invalid 0 0 0 0 0 0 0, 1

Invalid 1 0 0 1 0 0 0, 1

Invalid 1 1 0 1 1 0 0

Valid 1 1 0 1 1 0 1

Valid 1 2 0 1 2 0 0, 1

Valid 2 1 0 2 1 0 0, 1

(1) Not production tested.

(2) No hardware to detect illegal XTIMING configurations

Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-33.

Table 6-33. XINTF Clock Configurations

MODE SYSCLKOUT XTIMCLK XCLKOUT

1 SYSCLKOUT SYSCLKOUT

Example: 150 MHz 150 MHz 150 MHz

2 SYSCLKOUT 1/2 SYSCLKOUT

Example: 150 MHz 150 MHz 75 MHz

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