Texas-instruments TMS320C64x DSP Instrukcja Użytkownika Pobierz pdf (Strona 136)

Video Capture Registers

Video Capture Port3-74 SPRU629

3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL)

The transport stream interface clock initialization LSB register (TSICLKINITL)

is used to initialize the hardware counter to synchronize with the system time

clock. TSICLKINITL is shown in Figure 3–40 and described in Table 3–25.

On receiving the first packet containing a program clock reference (PCR) and

the PCR extension value, the DSP writes the 32 least-significant bits (LSBs)

of the PCR into TSICLKINITL. This initializes the counter to the system time

clock. TSICLKINITL should also be updated by the DSP whenever a disconti-

nuity in the PCR field is detected.

To ensure synchronization and prevent false compare detection, the software

should disable the system time clock interrupt (clear the STEN bit in TSICTL)

prior to writing to TSICLKINITL. All bits of the system time counter are initial-

ized whenever either TSICLKINITL or TSICLKINITM are written.

Figure 3–40. TSI Clock Initialization LSB Register (TSICLKINITL)

31 0

INPCR

R/W-0

Legend: R/W = Read/Write; -n = value after reset

Table 3–25. TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions

Description

Bit Field symval

†

Value

BT.656, Y/C Mode,

or Raw Data Mode

TSI Mode

31–0 INPCR OF(value) 0–FFFF FFFFh Not used. Initializes the 32 LSBs of the

system time clock.

†

For CSL implementation, use the notation VP_TSICLKINITL_INPCR_symval

1 2 ... 131 132 133 134 135 136 137 138 139 140 141 ... 305 306

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Texas-instruments TMS320C64x DSP Instrukcja Użytkownika Strona 136