Texas-instruments TMS320C645x DSP Instrukcja Użytkownika Pobierz pdf (Strona 94)

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5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)

EMAC Port Registers

The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 39 and described in

Table 39 .

Figure 39. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)

31 16

Reserved

R-0

15 8 7 6 5 4 3 2 1 0

Reserved TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0

MASK MASK MASK MASK MASK MASK MASK MASK

R-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0 R/WS-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Table 39. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions

Bit Field Value Description

31-8 Reserved 0 Reserved

7 TX7MASK Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

6 TX6MASK Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

5 TX5MASK Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

4 TX4MASK Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

3 TX3MASK Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

2 TX2MASK Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

1 TX1MASK Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

0 TX0MASK Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.

Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)94 SPRU975B – August 2006

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Texas-instruments TMS320C645x DSP Instrukcja Użytkownika Strona 94