Texas Instruments TMS320C642X Instrukcja Użytkownika

TMS320C642x DSPInter-Integrated Circuit (I2C) PeripheralUser's GuideLiterature Number: SPRUEN0DMarch 2011

d765PLL1I2CprescalerPrescaled module clock−−MUST be set to 6.7 to 13.3 MHzI2C input clockExternalinput clockRegister bits(ICPSC[IPSC])I2C clockdivider

WaitstateStart HIGHperiodSCL fromdevice #1SCL fromdevice #2Bus lineSCLwww.ti.comPeripheral ArchitectureThe prescaler (IPSC bit in ICPSC) must only be

Data linestable dataChange of dataallowedSDASCLSDASCLSTARTcondition (S)condition (P)STOPPeripheral Architecturewww.ti.com2.4.2 Data ValidityThe data o

SDASCLMSBAcknowledgementbit from slave(No-)Acknowledgementbit from receiver1 2 7 8 9 1 2 8 9Slave addressACKSTARTcondition (S)STOPcondition (P)R/W ACK

S11 1 1 1 0 A A7A A A A A A A AACK0118ACK1DatanACK1P1A A = 2 MSBs R/W 8 LSBs of slave addressDataDataS1DataACK ACK ACK P1n n n11117 n 7 n1 1 1 1 1 1 1

www.ti.comPeripheral Architecture2.7 Endianness ConsiderationsWhen the device is configured for big-endian mode, in order for the data to be placed in

Peripheral Architecturewww.ti.com2.9 NACK Bit GenerationWhen the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sen

10 0 010 0 01 11110Device #1 lost arbitrationand switches offBus lineSCLData fromdevice #1Data fromdevice #2Bus lineSDAwww.ti.comPeripheral Architectu

Peripheral Architecturewww.ti.com2.11 Reset ConsiderationsThe I2C peripheral has two reset sources: software reset and hardware reset.2.11.1 Software

www.ti.comPeripheral Architecture2.12.1 Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPUThe following initialization pro

2SPRUEN0D–March 2011Submit Documentation Feedback© 2011, Texas Instruments Incorporated

Peripheral Architecturewww.ti.com4. Enable the desired interrupt you need to receive by setting the desired interrupt bit field within ICIMRto enable

www.ti.comPeripheral Architecture2.13 Interrupt SupportThe is capable of interrupting the DSP CPU. The CPU can determine which I2C events caused thein

Registerswww.ti.com2.16 Emulation ConsiderationsThe response of the I2C events to emulation suspend events (such as halts and breakpoints) is controll

www.ti.comRegisters3.1 I2C Own Address Register (ICOAR)The I2C own address register (ICOAR) is used to specify its own slave address, which distinguis

Registerswww.ti.com3.2 I2C Interrupt Mask Register (ICIMR)The I2C interrupt mask register (ICIMR) is used to individually enable or disable I2C interr

www.ti.comRegisters3.3 I2C Interrupt Status Register (ICSTR)The I2C interrupt status register (ICSTR) is used to determine which interrupt has occurre

Registerswww.ti.comTable 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued)Bit Field Value Description10 XSMT Transmit shift regi

www.ti.comRegistersTable 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued)Bit Field Value Description1 NACK No-acknowledgment in

Registerswww.ti.com3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH)When the I2C is a master, the prescaled module clock is divided down for use as

www.ti.comRegisters3.5 I2C Data Count Register (ICCNT)The I2C data count register (ICCNT) is used to indicate how many data words to transfer when the

Preface ... 61 Int

Registerswww.ti.com3.6 I2C Data Receive Register (ICDRR)The I2C data receive register (ICDRR) is used to read the receive data. The ICDRR can receive

www.ti.comRegisters3.8 I2C Data Transmit Register (ICDXR)The CPU or EDMA writes transmit data to the I2C data transmit register (ICDXR). The ICDXR can

Registerswww.ti.com3.9 I2C Mode Register (ICMDR)The I2C mode register (ICMDR) contains the control bits of the I2C.The I2C mode register (ICMDR) is sh

www.ti.comRegistersTable 14. I2C Mode Register (ICMDR) Field Descriptions (continued)Bit Field Value Description10 MST Master mode bit. MST determines

Registerswww.ti.comTable 14. I2C Mode Register (ICMDR) Field Descriptions (continued)Bit Field Value Description2-0 BC 0-7h Bit count bits. BC defines

ICDRR ICRSR01ICSARICOAR01ICDXRICXSR0100DLBSCL_INSCL_OUTAddress/dataTo internal I2C logicFrom internal I2C logicTo internal I2C logicTo ARM CPU or EDMA

Registerswww.ti.com3.10 I2C Interrupt Vector Register (ICIVR)The I2C interrupt vector register (ICIVR) is used by the CPU to determine which event gen

www.ti.comRegisters3.11 I2C Extended Mode Register (ICEMDR)The I2C extended mode register (ICEMDR) is used to indicate which condition generates a tra

Registerswww.ti.com3.12 I2C Prescaler Register (ICPSC)The I2C prescaler register (ICPSC) is used for dividing down the I2C input clock to obtain the d

www.ti.comRegisters3.13 I2C Peripheral Identification Register (ICPID1)The I2C peripheral identification registers (ICPID1) contain identification dat

www.ti.comList of Figures1 I2C Peripheral Block Diagram... 8

www.ti.comAppendix A Revision HistoryTable 22 lists the changes made since the previous version of this document.Table 22. Document Revision HistoryRe

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

www.ti.comList of Tables1 Operating Modes of the I2C Peripheral ... 152 W

PrefaceSPRUEN0D–March 2011Read This FirstAbout This ManualThis document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Dig

User's GuideSPRUEN0D–March 2011Inter-Integrated Circuit (I2C) Peripheral1 IntroductionThis document describes the operation of the inter-integrat

ICXSR ICDXRICRSR ICDRRClocksynchronizerPrescalerNoise filtersArbitratorI2C INTICREVTPeripheral data busInterruptto CPUSync events toEDMA controllerSDA

TI deviceI2CI2CEPROMI2CI2CTI deviceVDDPull-upresistorsSerial data (SDA)Serial clock (SCL)controllerwww.ti.comPeripheral Architecture2 Peripheral Archi