Texas Instruments TMS320DM644x Instrukcja Użytkownika

TMS320DM644x DMSoCMultimedia Card (MMC)/Secure Digital (SD)Card ControllerUser's GuideLiterature Number: SPRUE30BSeptember 2006

www.ti.comStatusandregistersDMA requestsInterruptsARM CPUFIFOMMC/SDinterfaceCLKdividerMMC/SDcardinterface1.4 Supported Use Case Statement1.5 Industry

www.ti.comNative packetsNativesignalsCMDCLKDAT0 or DAT0−3MMC/SDcontrollerARMEDMAMemoryMMCs or SD cardsSD_CLKSD_CMDSD_DATA0SD_DATA1SD_DATA2SD_DATA3MMC/

www.ti.com2.1 Clock ControlMMCCLK(CLKRT)Function clock forMMC/SD controllerMMC/SD controllerMMC/SDinput clockcardMMC/SDMemory clockon CLK pinPeriphera

www.ti.com2.2 Signal Descriptions2.3 Protocol Descriptions2.3.1 MMC/SD Mode Write SequencePeripheral ArchitectureTable 1 shows the MMC/SD controller p

www.ti.com2 CRC bytesBusylowStartbitEndbitStartbitEndbitCMDDataCLK2.3.2 MMC/SD Mode Read SequencePeripheral ArchitectureFigure 5. MMC/SD Mode Write Se

www.ti.comStartbitEndbitCMDDataCLK1 transfersource bit2 CRCbytes2.4 Data Flow in the Input/Output FIFOPeripheral ArchitectureFigure 6. MMC/SD Mode Rea

www.ti.comARM/EDMA reads/writesWrite ReadFIFO8−bit x 32(256−bit)FIFOEDMA event128 or 256 bit128 or 256 bitEDMA eventEDMA eventthe end of atransferPoin

www.ti.com2.5 Data Flow in the Data Registers (MMCDRR and MMCDXR)1st2nd3rd4th34th 3rd 2nd 1stSupport byten = ”1111”Support byten = ”0111”3rd2nd1st33rd

www.ti.com1st2nd3rd4th34th3rd2nd1stSupport byten = ”1111”Support byten = ”1110”3rd2nd1st33rd2nd1stSupport byten = ”1100”1st2nd32nd1st0Support byten =

www.ti.com2.6 FIFO Operation During Card Read Operation2.6.1 EDMA Reads2.6.2 CPU ReadsPeripheral ArchitectureThe FIFO controller manages the activitie

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www.ti.comFIFO Check1/StartFIFOfull?Counter=FIFOLEV?YesNoCapture data,no DMA pendingIncrement counterNoYesGenerate DMAReset counterFIFO check 2YesNo?f

www.ti.com2.7 FIFO Operation During Card Write Operation2.7.1 EDMA Writes2.7.2 CPU WritesPeripheral ArchitectureThe FIFO controller manages the activi

www.ti.comFIFO Check1/StartFIFOfull?Counter=FIFOLEV?YesNoCapture data,no DMA pendingIncrement counterNoYesGenerate DMAReset counterFIFO check 2YesNo?f

www.ti.com2.8 Reset Considerations2.8.1 Software Reset Considerations2.8.2 Hardware Reset Considerations2.9 Initialization2.9.1 MMC/SD Controller Init

www.ti.com2.9.3 Initializing the Clock Controller Registers (MMCCLK)2.9.4 Initialize the Interrupt Mask Register (MMCIM)2.9.5 Initialize the Time-Out

www.ti.com2.9.7 Monitoring Activity in the MMC/SD Mode2.9.7.1 Determining Whether New Data is Available in MMCDRR2.9.7.2 Verifying that MMCDXR is Read

www.ti.com2.9.7.8 Determining When Last Data has Been Written to Card (SanDisk SD cards)2.9.7.9 Checking For a Data Transmit Empty Condition2.9.7.10 C

www.ti.com2.10 Interrupt Support2.10.1 Interrupt Events and Requests2.10.2 Interrupt MultiplexingPeripheral ArchitectureThe MMC/SD controller generate

www.ti.com2.11 DMA Event Support2.12 Power Management2.13 Emulation ConsiderationsPeripheral ArchitectureThe MMC/SD controller is capable of generatin

www.ti.com3 Procedures for Common Operations3.1 Card Identification Operation3.1.1 MMC Card Identification ProcedureProcedures for Common OperationsBe

ContentsPreface ... 71 Int

www.ti.com3.1.2 SD Card Identification ProcedureProcedures for Common OperationsFigure 12. MMC Card Identification ProcedureThe SD card identification

www.ti.comProcedures for Common Operations6. Repeat step 4 and step 5 to identify and retrieve relative addresses from all remaining SD cards untilno

www.ti.com3.2 MMC/SD Mode Single-Block Write Operation Using CPUProcedures for Common OperationsTo perform a single-block write, the block length must

www.ti.comARG HIGHRCA ADDRESS HIGHSTATUS 0NEXT DATA BYTEDATA TXMMC controllerregister contentMMC controllerregisterRCA ADDRESS LOWARG LOWSEL/DESEL. CA

www.ti.com3.3 MMC/SD Mode Single-Block Write Operation Using the EDMA3.4 MMC/SD Mode Single-Block Read Operation Using the CPUProcedures for Common Op

www.ti.comARG HIGHRCA ADDRESS HIGHSTATUS 0NEXT DATA BYTEDATA TXMMC controllerregister contentMMC controllerregisterRCA ADDRESS LOWARG LOWSEL/DESEL. CA

www.ti.com3.6 MMC/SD Mode Multiple-Block Write Operation Using CPUProcedures for Common OperationsTo perform a multiple-block write, the same block le

www.ti.comARG HIGHRCA ADDRESS HIGHSTATUS 0NEXT DATA BYTEDATA TXMMC controllerregister contentMMC controllerregisterRCA ADDRESS LOWARG LOWSEL/DESEL. CA

www.ti.com3.7 MMC/SD Mode Multiple-Block Write Operation Using EDMA3.8 MMC/SD Mode Multiple-Block Read Operation Using CPUProcedures for Common Operat

www.ti.comARG HIGHRCA ADDRESS HIGHSTATUS 0NEXT DATA BYTEDATA TXMMC controllerregister contentMMC controllerregisterRCA ADDRESS LOWARG LOWSEL/DESEL. CA

4.13 MMC Command Register (MMCCMD) ... 524.14 MMC Argument Register (MMCARGHL) ...

www.ti.com4 RegistersRegistersTable 5 lists the memory-mapped registers for the multimedia card/secure digital (MMC/SD) cardcontroller. See the device

www.ti.com4.1 MMC Control Register (MMCCTL)RegistersThe MMC control register (MMCCTL) is used to enable or configure various modes of the MMC controll

www.ti.com4.2 MMC Memory Clock Control Register (MMCCLK)RegistersThe MMC memory clock control register (MMCCLK) is used to:• Select whether the CLK pi

www.ti.com4.3 MMC Status Register 0 (MMCST0)RegistersThe MMC status register 0 (MMCST0) records specific events or errors. The transition from 0 to 1

www.ti.comRegistersTable 8. MMC Status Register 0 (MMCST0) Field Descriptions (continued)Bit Field Value Description5 CRCWR Write-data CRC error.0 A w

www.ti.com4.4 MMC Status Register 1 (MMCST1)RegistersThe MMC status register 1 (MMCST1) records specific events or errors. There are no interruptsasso

www.ti.com4.5 MMC Interrupt Mask Register (MMCIM)RegistersThe MMC interrupt mask register (MMCIM) is used to enable (bit = 1) or disable (bit = 0) sta

www.ti.com4.6 MMC Response Time-Out Register (MMCTOR)RegistersTable 10. MMC Interrupt Mask Register (MMCIM) Field Descriptions (continued)Bit Field Va

www.ti.com4.7 MMC Data Read Time-Out Register (MMCTOD)RegistersThe MMC data read time-out register (MMCTOD) defines how long the MMC controller waits

www.ti.com4.8 MMC Block Length Register (MMCBLEN)RegistersThe MMC block length register (MMCBLEN) specifies the data block length in bytes. This value

List of Figures1 MMC/SD Card Controller Block Diagram ... 102 MMC/SD Contr

www.ti.com4.9 MMC Number of Blocks Register (MMCNBLK)4.10 MMC Number of Blocks Counter Register (MMCNBLC)RegistersThe MMC number of blocks register (M

www.ti.com4.11 MMC Data Receive Register (MMCDRR)4.12 MMC Data Transmit Register (MMCDXR)RegistersThe MMC data receive register (MMCDRR) is used for s

www.ti.com4.13 MMC Command Register (MMCCMD)RegistersNote: Writing to the MMC command register (MMCCMD) causes the MMC controller to send theprogramme

www.ti.comRegistersTable 18. MMC Command Register (MMCCMD) Field Descriptions (continued)Bit Field Value Description12 STRMTP Stream enable.0 If WDATX

www.ti.com4.14 MMC Argument Register (MMCARGHL)RegistersNote: Do not modify the MMC argument register (MMCARGHL) while it is being used for anoperatio

www.ti.com4.15 MMC Response Registers (MMCRSP0-MMCRSP7)RegistersEach command has a preset response type. When the MMC controller receives a response,

www.ti.comRegistersTable 21. R1, R3, R4, R5, or R6 Response (48 Bits)Bit Position of Response Register47-40 MMCCIDX39-24 MMCRSP723-8 MMCRSP67-0 MMCRSP

www.ti.com4.16 MMC Data Response Register (MMCDRSP)4.17 MMC Command Index Register (MMCCIDX)RegistersAfter the MMC controller sends a data block to a

www.ti.com4.18 MMC FIFO Control Register (MMCFIFOCTL)RegistersThe MMC FIFO control register (MMCFIFOCTL) is shown in Figure 39 and described in Table

www.ti.comAppendix A Revision HistoryAppendix ATable A-1 lists the changes made since the previous version of this document.Table A-1. Document Revisi

List of Tables1 MMC/SD Controller Pins Used in Each Mode ... 132 MMC/SD Mode Wr

www.ti.comAppendix ARevision History60 SPRUE30B – September 2006Submit Documentation Feedback

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvemen

PrefaceSPRUE30B – September 2006Read This FirstAbout This ManualThis manual describes the multimedia card (MMC)/secure digital (SD) card controller in

www.ti.comRelated Documentation From Texas InstrumentsSPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal pr

1 Introduction1.1 Purpose of the Peripheral1.2 Features1.3 Functional Block DiagramUser's GuideSPRUE30B – September 2006Multimedia Card (MMC)/Sec