Texas Instruments TMS320C642x DSP Instrukcja Użytkownika Strona 1

TMS320C642x DSPDDR2 Memory ControllerUser's GuideLiterature Number: SPRUEM4ANovember 2007

www.ti.com2.1.2 Clock Configuration2.1.3 DDR2 Memory Controller Internal Clock Domains2.2 Memory MapPeripheral ArchitectureThe frequency of PLL2_SYSCL

www.ti.com2.3 Signal DescriptionsDDR_D[31:0]DDR2memorycontrollerDDR_CLKDDR_CLKDDR_CSDDR_CKEDDR_RASDDR_WEDDR_DQM[3:0]DDR_CASDDR_BA[2:0]DDR_DQS[3:0]DDR_

www.ti.com2.4 Protocol Description(s)Peripheral ArchitectureThe DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 3 . Table 4 sh

www.ti.com2.4.1 Refresh ModeDDR_CLKDDR_CKEDDR_CSDDR_RASDDR_CASDDR_WEDDR_A[12:0]DDR_BA[2:0]DDR_DQM[3:0]RFRDDR_CLKPeripheral ArchitectureThe DDR2 memory

www.ti.com2.4.2 Deactivation (DCAB and DEAC)DDR_CLKDDR_CKEDDR_CSDDR_RASDDR_WEDDR_A[12,11, 9:0]DDR_BA[2:0]DDR_DQM[3:0]DCABDDR_A[10]DDR_CASDDR_CLKPeriph

www.ti.comDDR_CLKDDR_CKEDDR_CSDDR_RASDDR_WEDDR_A[12,11, 9:0]DDR_BA[2:0]DDR_DQM[3:0]DEACDDR_A[10]DDR_CASDDR_CLKPeripheral ArchitectureThe DEAC command

www.ti.com2.4.3 Activation (ACTV)DDR_CLKDDR_CKEDDR_CSDDR_RASDDR_WEDDR_BA[2:0]DDR_DQM[3:0]ACTVDDR_A[12:0]DDR_CASBANKROWDDR_CLKPeripheral ArchitectureTh

www.ti.com2.4.4 READ CommandDDR_CLKDDR_CKEDDR_CSDDR_WEDDR_CASDDR_DQM[3:0]DDR_D[31:0]DDR_A[12:0]DDR_RASDDR_DQS[3:0]COLBANKDDR_A[10]DDR_BA[2:0]CAS Laten

www.ti.com2.4.5 Write (WRT) CommandDDR_CLKDDR_CKEDDR_CSDDR_WEDDR_CASDDR_DQM[3:0]DDR_D[31:0]DDR_A[12:0]DDR_RASDDR_DQS[3:0]COLBANKDDR_A[10]DDR_BA[2:0]DQ

www.ti.com2.4.6 Mode Register Set (MRS and EMRS)DDR_CLKDDR_CKEDDR_CSDDR_RASDDR_WEDDR_BA[2:0]COLMRS/EMRSDDR_A[12:0]DDR_CASBANKDDR_CLKPeripheral Archite

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www.ti.com2.5 Memory Width and Byte AlignmentDDR2 memory controller data busDDR_D[31:24]DDR_D[23:16] DDR_D[15:8] DDR_D[7:0]32-bit memory device16-bit

www.ti.com2.6 Endianness SupportPeripheral ArchitectureThe DDR2 memory controller supports both big-endian and little-endian operating modes. The endi

www.ti.com2.7 Address MappingPeripheral ArchitectureThe DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. Thisstatem

www.ti.comPeripheral ArchitectureTable 9. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAMSDBCR Bit Logical Address(1)IBANK PAGESIZE 31 30 2

www.ti.comCol. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col. MRow 0, bank 0Row 0, bank 1Row 0, bank 2Row 0, bank PRow 1, bank 1Row 1, bank 0Row 1, bank

www.ti.com0 1 2 3 MBank 0Row 0Row 1Row 2Row NCol lColColCoRow 0Row NRow 1Row 2CCBank 1l l0 21ooC Cl l3 Mo oRow 0Row NRow 1Row 2CCBank 2l l0 21oollllRo

www.ti.com2.8 DDR2 Memory Controller InterfaceCommand/DataSchedulerCommand FIFOWrite FIFORead FIFORegistersCommandto MemoryWrite Datato MemoryRead Dat

www.ti.com2.8.1 Command Ordering and Scheduling, Advanced ConceptPeripheral ArchitectureThe DDR2 memory controller performs command re-ordering and sc

www.ti.com2.8.2 Command Starvation2.8.3 Possible Race ConditionPeripheral ArchitectureThe reordering and scheduling rules listed above may lead to com

www.ti.com2.9 Refresh Scheduling2.10 Self-Refresh ModePeripheral ArchitectureThe DDR2 memory controller issues autorefresh (REFR) commands to DDR2 SDR

ContentsPreface ... 61 Int

www.ti.com2.11 Reset ConsiderationsDDR2memorycontrollerregistersHardReset fromPLLC1StatemachineVRSTVCTL_RSTDDRPSCPeripheral ArchitectureOnce in self-r

www.ti.com2.12 VTP IO Buffer Calibration2.13 Auto-Initialization SequencePeripheral ArchitectureThe DDR2 memory controller is able to control the impe

www.ti.com2.13.1 Initializing Configuration RegistersPeripheral ArchitectureTable 14. DDR2 SDRAM Configuration by MRS CommandDDR2 MemoryController DDR

www.ti.com2.13.2 Initializing Following Device Power Up and Device RESETPeripheral ArchitectureCAUTIONThe following power-up sequence is preliminary a

www.ti.com2.14 Interrupt Support2.15 DMA Event Support2.16 Power ManagementPLLC2CLKSTOP_REQDDRPSCCLKSTOP_ACKMODCLKMODRSTLRSTDDR2memorycontrollerVCLKST

www.ti.com2.16.1 DDR2 Memory Controller Clock Stop Procedure2.17 Emulation ConsiderationsPeripheral ArchitectureCAUTIONThe following clock stop proced

www.ti.com3 Supported Use Cases3.1 Connecting the DDR2 Memory Controller to DDR2 Memory3.2 Configuring Memory-Mapped Registers to Meet DDR2-400 Specif

www.ti.comDDR_CLKDDR_CLKDDR_CKEDDR_CSDDR_WEDDR_RASDDR_CASDDR_DQM[0]DDR_DQM[1]DDR_DQS[0]DDR_DQS[1]DDR_BA[2:0]DDR_A[12:0]DDR_D[15:0]DDR_DQM[2]DDR_DQM[3]

www.ti.com3.2.1 Configuring SDRAM Bank Configuration Register (SDBCR)3.2.2 Configuring SDRAM Refresh Control Register (SDRCR)Supported Use CasesThe SD

www.ti.com3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2)Supported Use CasesThe SDRAM timing register (SDTIMR) and SDRAM timing register

List of Figures1 Data Paths to DDR2 Memory Controller ... 82 DDR2 Memor

www.ti.com3.2.4 Configuring DDR PHY Control Register (DDRPHYCR)Supported Use CasesThe DDR PHY control register (DDRPHYCR) contains a read latency (REA

www.ti.com4 DDR2 Memory Controller RegistersDDR2 Memory Controller RegistersTable 22 lists the memory-mapped registers related to the DDR2 memory cont

www.ti.com4.1 SDRAM Status Register (SDRSTAT)DDR2 Memory Controller RegistersThe SDRAM status register (SDRSTAT) is shown in Figure 19 and described i

www.ti.com4.2 SDRAM Bank Configuration Register (SDBCR)DDR2 Memory Controller RegistersThe SDRAM bank configuration register (SDBCR) contains fields t

www.ti.comDDR2 Memory Controller RegistersTable 26. SDRAM Bank Configuration Register (SDBCR) Field Descriptions (continued)Bit Field Value Descriptio

www.ti.com4.3 SDRAM Refresh Control Register (SDRCR)DDR2 Memory Controller RegistersThe SDRAM refresh control register (SDRCR) is used to configure th

www.ti.com4.4 SDRAM Timing Register (SDTIMR)DDR2 Memory Controller RegistersThe SDRAM timing register (SDTIMR) configures the DDR2 memory controller t

www.ti.com4.5 SDRAM Timing Register 2 (SDTIMR2)DDR2 Memory Controller RegistersLike the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (S

www.ti.com4.6 Peripheral Bus Burst Priority Register (PBBPR)DDR2 Memory Controller RegistersThe peripheral bus burst priority register (PBBPR) helps p

www.ti.com4.7 Interrupt Raw Register (IRR)DDR2 Memory Controller RegistersThe interrupt raw register (IRR) displays the raw status of the interrupt. I

List of Tables1 PLLC2 Configuration ... 102 DDR2 M

www.ti.com4.8 Interrupt Masked Register (IMR)DDR2 Memory Controller RegistersThe interrupt masked register (IMR) displays the status of the interrupt

www.ti.com4.9 Interrupt Mask Set Register (IMSR)DDR2 Memory Controller RegistersThe interrupt mask set register (IMSR) enables the DDR2 memory control

www.ti.com4.10 Interrupt Mask Clear Register (IMCR)DDR2 Memory Controller RegistersThe interrupt mask clear register (IMCR) disables the DDR2 memory c

www.ti.com4.11 DDR PHY Control Register (DDRPHYCR)DDR2 Memory Controller RegistersThe DDR PHY control register (DDRPHYCR) configures the DDR2 memory c

www.ti.com4.12 VTP IO Control Register (VTPIOCR)DDR2 Memory Controller RegistersThe VTP IO control register (VTPIOCR) is used to control the calibrati

www.ti.com4.13 DDR VTP Register (DDRVTPR)4.14 DDR VTP Enable Register (DDRVTPER)DDR2 Memory Controller RegistersThe DDR VTP register (DDRVTPR) is used

www.ti.comAppendix A Revision HistoryAppendix ATable A-1 lists the changes made since the previous version of this document.Table A-1. Document Revisi

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,improvemen

PrefaceSPRUEM4A – November 2007Read This FirstAbout This ManualThis document describes the DDR2 memory controller in the TMS320C642x Digital Signal Pr

1 Introduction1.1 Purpose of the Peripheral1.2 FeaturesUser's GuideSPRUEM4A – November 2007DDR2 Memory ControllerThis document describes the DDR2

www.ti.com1.3 Functional Block DiagramSCRDDR2memorycontrollerBUS BUSExternalDDR2 SDRAMDSPMasterperipheralsEDMAVPSS1.4 Supported Use Case Statement1.5

www.ti.com2 Peripheral Architecture2.1 Clock Control2.1.1 Clock SourceDDR2memorycontroller/2PLLC2/3PLLC1X2_CLKVCLKDDR_CLKDDR_CLKPLL2_SYSCLK1SYSCLK2Per