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GPxDAT (read)
Input
Qualification
GPxMUX1/2
High Impedance
Output Control
GPIOx pin
XRS
0 = Input, 1 = Output
Low Power
Modes Block
GPxDIR (latch)
Peripheral 2 Input
Peripheral 3 Input
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
Peripheral 1 Output Enable
Peripheral 2 Output Enable
Peripheral 3 Output Enable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral 1 Input
N/C
GPxPUD
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
= Default at Reset
PIE
External Interrupt
MUX
Asynchronous
path
Asynchronous path
TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230L–OCTOBER 2003–REVISED DECEMBER 2009
www.ti.com
4.11 GPIO MUX
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in Figure 4-16. Because of the open drain capabilities of the I2C pins, the GPIO MUX block
diagram for these pins differ. See the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts
Reference Guide (literature number SPRU712) for details.
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
Figure 4-16. GPIO MUX Block Diagram
82 Peripherals Copyright © 2003–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802
TMS320C2801 TMS320F28016 TMS320F28015
- Data Manual 1
- Contents 2
- Contents 3 3
- List of Figures 5
- List of Tables 7
- Digital Signal Processors 9
- 1.2 Getting Started 10
- 2 Introduction 11
- 2.1 Pin Assignments 14
- Introduction 15 15
- Introduction 17 17
- 2.2 Signal Descriptions 19
- See Table 2-2 for details 24
- 3 Functional Overview 25
- 3.1 Memory Maps 26
- Figure 3-3. F2808 Memory Map 27
- Figure 3-4. F2806 Memory Map 28
- Table 3-6. Wait-states 33
- 3.2 Brief Descriptions 34
- 3.2.1 C28x CPU 34
- 3.2.3 Peripheral Bus 34
- 3.2.5 Flash 35
- 3.2.6 ROM 35
- 3.2.7 M0, M1 SARAMs 35
- 3.2.8 L0, L1, H0 SARAMs 36
- 3.2.9 Boot ROM 36
- 3.2.10 Security 37
- 3.2.20 Control Peripherals 39
- 3.3 Register Map 40
- 3.5 Interrupts 42
- Functional Overview 43 43
- 3.5.1 External Interrupts 45
- 3.6 System Control 46
- 3.6.1 OSC and PLL Block 47
- PLLSTS[PLLLOCKS] = 1 49
- 3.6.2 Watchdog Block 51
- 3.7 Low-Power Modes Block 52
- 4 Peripherals 53
- Peripherals 57 57
- 4.3 Hi-Resolution PWM (HRPWM) 58
- Peripherals 59 59
- Value Register 60
- Peripherals 63 63
- 4.6.2 ADC Registers 67
- Table 4-7. CAN Register Map 72
- Peripherals 73 73
- Peripherals 75 75
- Table 4-13 77
- Table 4-10. SPI-A Registers 77
- Table 4-11. SPI-B Registers 77
- Table 4-12. SPI-C Registers 78
- Table 4-13. SPI-D Registers 78
- Peripherals 79 79
- Table 4-14. I2C-A Registers 81
- 4.11 GPIO MUX 82
- Table 4-15. GPIO Registers 83
- 5 Device Support 86
- 5.2 Documentation Support 88
- Device Support 89 89
- Device Support 91 91
- 6 Electrical Specifications 93
- 6.4 Current Consumption 95
- SYSCLKOUT 97
- 100-MHz SYSCLKOUT 98
- Device Power Vs SYSCLKOUT 101
- Submit Documentation Feedback 102
- 6.6.2 Test Load Circuit 103
- 6.6.3 Device Clock Table 104
- 6.8 Power Sequencing 106
- Figure 6-8. Power-on Reset 107
- Figure 6-9. Warm Reset 108
- 6.9.1 GPIO - Output Timing 109
- 6.9.2 GPIO - Input Timing 110
- XINT2_ADCSOC signal as well 111
- 6.10.2 Trip-Zone Input Timing 115
- Table 6-33. I2C Timing 118
- (1) (2) (3) (4) (5) 119
- 6.10.6 SPI Slave Mode Timing 123
- (1) (2) (3) (4) 124
- variation ±4 LSB 125
- SINAD * 1.76 130
- 6.12 Flash Timing 131
- 6.13 ROM Timing (C280x only) 132
- 7.1 Migration Issues 133
- 8 Revision History 134
- 9 Mechanical Data 135
- PACKAGE OPTION ADDENDUM 137
- MECHANICAL DATA 141
- MECHANICAL DATA 143
- IMPORTANT NOTICE 144
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