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TMS320C6455/C6454 DSPDDR2 Memory ControllerUser's GuideLiterature Number: SPRU970GDecember 2005– Revised June 2011

L1 S1 M1 D1Data path ARegister file ARegister file BD2Data path BS2M2 L2L1 data memory controllerCache controlMemory protectionInterruptand exceptionc

www.ti.comPeripheral Architecture2 Peripheral ArchitectureThe DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices ands

DED[31:0]DDR2MemoryControllerDDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWEDSDDQM[3:0]DSDCASDBA[2:0]DSDDQS[3:0]DEA[13:0]VREFSSTLDSDDQGATE[3:0]DSDDQS[3:0]DE

www.ti.comPeripheral Architecture2.4 Protocol Description(s)The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2. Table 3 sho

COLMRS/EMRSBANKDDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWEDSDCASDBA[2:0]DEA[13:0]Peripheral Architecturewww.ti.com2.4.1 Mode Register Set (MRS and EMRS)

REFRDDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWEDSDDQM[3:0]DSDCASDBA[2:0]DEA[13:0]www.ti.comPeripheral Architecture2.4.2 Refresh ModeThe DDR2 memory cont

ACTVBANKROWDDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWEDSDDQM[3:0]DSDCASDBA[2:0]DEA[13:0]Peripheral Architecturewww.ti.com2.4.3 Activation (ACTV)The DDR2

DCABDDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWEDSDDQM[3:0]DSDCASDBA[2:0]DEA[13:11,9:0]DEA[10]www.ti.comPeripheral Architecture2.4.4 Deactivation (DCAB

DEACDDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWEDSDDQM[3:0]DSDCASDBA[2:0]DEA[13:11,9:0]DEA[10]Peripheral Architecturewww.ti.comThe DEAC command closes a

DED[31:0]DSDDQS[3:0]COLBANKDEA[10]CASLatencyD0D1 D2D3D4D5D6D7DDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWEDSDDQM[3:0]DSDCASDBA[2:0]DEA[13:0]www.ti.comPer

2SPRU970G–December 2005–Revised June 2011Submit Documentation FeedbackCopyright © 2005–2011, Texas Instruments Incorporated

DED[31:0]DSDDQS[3:0]COLBANKDQM7SampleD0D1 D2D3D4D5D6D7DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8WriteLatencyDEA[10]DDR2CLKOUTDDR2CLKOUTDCE0DSDCKEDSDRASDSDWED

DDR2 memory controller data busDED[31:24](Byte Lane 3)DED[23:16](Byte Lane 2)DED[15:8](Byte Lane 1)DED[7:0](Byte Lane 0)32-bit memory device16-bit mem

Peripheral Architecturewww.ti.comFigure 11 and Figure 12 show how the logical address bits map to the row, column, bank, and chip selectbits all combi

Col. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col. MRow 0, bank 0Row 0, bank 1Row 0, bank 2Row 0, bank PRow 1, bank 1Row 1, bank 0Row 1, bank 2Row 1, ba

0 1 2 3 MBank 0Row 0Row 1Row 2Row NCol lColColCoRow 0Row NRow 1Row 2CCBank 1l l0 21ooC Cl l3Mo oRow 0Row NRow 1Row 2CCBank 2l l0 21oollllRow NRow 2Row

Command/DataSchedulerCommand FIFOWrite FIFORead FIFORegistersCommandto MemoryWrite Datato MemoryRead DatafromMemoryCommandDataEDMA BUSwww.ti.comPeriph

Peripheral Architecturewww.ti.comNext, the DDR2 memory controller examines each of the commands selected by the individual mastersand performs the fol

www.ti.comPeripheral Architecture2.7.3 Possible Race ConditionA race condition may exist when certain masters write data to the DDR2 memory controller

Peripheral Architecturewww.ti.com2.9 Self-Refresh ModeSetting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the

www.ti.comPeripheral Architecture• Following a write to the two least-significant bytes in the SDRAM configuration register (SDCFG); seeSection 2.11.3

ContentsPreface ...

Peripheral Architecturewww.ti.com2.11.2 DDR2 SDRAM Initialization After ResetAfter a hard or a soft reset, the DDR2 memory controller will automatical

www.ti.comUsing the DDR2 Memory Controller3 Using the DDR2 Memory ControllerThe following sections show various ways to connect the DDR2 memory contro

DDR2CLKOUTDDR2CLKOUTDSDCKEDCE0DSDWEDSDRASDSDCASDSDDQM0DSDDQM1DSDDQS0DSDDQS1DBA[2:0]DEA[13:0]DED[15:0]ODT0DSDDQS0DSDDQS1CKCKCKECSWERASCASLDMLDQSUDQSBA[

DDR2CLKOUTDDR2CLKOUTDSDCKEDCE0DSDWEDSDRASDSDCASDSDDQM0DSDDQM1DSDDQS0DSDDQS1DBA[2:0]DEA[13:0]DED[15:0]VREFSSTLODT0DSDDQS0DSDDQS1CKCKCKECSWERASCASLDMUDM

DDR2CLKOUTDDR2CLKOUTDSDCKEDCE0DSDWEDSDRASDSDCASDSDDQM0DSDDQM1DSDDQS0DSDDQS1DBA[2:0]DEA[13:0]DED[7:0]VREFSSTLODT0DSDDQS0DSDDQS1CKCKCKECSWERASCASDMDQSRD

www.ti.comUsing the DDR2 Memory Controller3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM SpecificationsThe DDR2 memory controller

Using the DDR2 Memory Controllerwww.ti.comTable 12 displays the DDR2-533 refresh rate specification.Table 12. DDR2 Memory Refresh SpecificationSymbol

www.ti.comUsing the DDR2 Memory ControllerTable 15. SDTIM2 ConfigurationDDR2 SDRAM DataRegister Field Sheet Parameter Data Sheet Formula (Register Fie

DDR2 Memory Controller Registerswww.ti.com4 DDR2 Memory Controller RegistersTable 17 lists the memory-mapped registers for the DDR2 memory controller.

www.ti.comDDR2 Memory Controller Registers4.1 Module ID and Revision Register (MIDR)The Module ID and Revision register (MIDR) is shown in Figure 19 a

www.ti.comList of Figures1 Device Block Diagram ... 1

DDR2 Memory Controller Registerswww.ti.com4.2 DDR2 Memory Controller Status Register (DMCSTAT)The DDR2 memory controller status register (DMCSTAT) is

www.ti.comDDR2 Memory Controller Registers4.3 SDRAM Configuration Register (SDCFG)The SDRAM configuration register (SDCFG) contains fields that progra

DDR2 Memory Controller Registerswww.ti.comTable 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued)Bit Field Value Description11-9

www.ti.comDDR2 Memory Controller Registers4.4 SDRAM Refresh Control Register (SDRFC)The SDRAM refresh control register (SDRFC) is used to configure th

DDR2 Memory Controller Registerswww.ti.com4.5 SDRAM Timing 1 Register (SDTIM1)The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controll

www.ti.comDDR2 Memory Controller RegistersTable 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued)Bit Field Value Description5-3 T_RR

DDR2 Memory Controller Registerswww.ti.com4.6 SDRAM Timing 2 Register (SDTIM2)Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (

www.ti.comDDR2 Memory Controller Registers4.7 Burst Priority Register (BPRIO)The Burst Priority Register (BPRIO) helps prevent command starvation with

DDR2 Memory Controller Registerswww.ti.com4.8 DDR2 Memory Controller Control Register (DMCCTL)The DDR2 memory controller control register (DMCCTL) res

www.ti.comRevision HistoryRevision HistoryThis revision history highlights the technical changes made to the document in this revision.See Additions/M

www.ti.comList of Tables1 DDR2 Memory Controller Signal Descriptions... 122 DDR2

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

6List of Tables SPRU970G– December 2005– Revised June 2011Submit Documentation FeedbackCopyright © 2005–2011, Texas Instruments Incorporated

PrefaceSPRU970G– December 2005– Revised June 2011Read This FirstAbout This ManualThis document describes the DDR2 memory controller in the TMS320C6455

8Read This First SPRU970G– December 2005– Revised June 2011Submit Documentation FeedbackCopyright © 2005–2011, Texas Instruments Incorporated

User's GuideSPRU970G– December 2005– Revised June 2011C6455/C6454 DDR2 Memory Controller1 Introduction1.1 Purpose of the PeripheralThe DDR2 memor