Texas-instruments TMS320DM36X Instrukcja Użytkownika

TMS320DM36x Digital Media System-on-Chip(DMSoC)Ethernet Media Access Controller (EMAC)User's GuideLiterature Number: SPRUFI5BMarch 2009–Revised D

PrefaceSPRUFI5B–March 2009–Revised December 2010Read This FirstAbout This ManualThis document provides a functional description of the Ethernet Media

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)The MAC interrupt mask set register (MA

www.ti.comEthernet Media Access Controller (EMAC) Registers5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register(RXMBPENABLE)The receiv

Ethernet Media Access Controller (EMAC) Registerswww.ti.comTable 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)Fiel

www.ti.comEthernet Media Access Controller (EMAC) RegistersTable 58. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)Fiel

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.22 Receive Unicast Enable Set Register (RXUNICASTSET)The receive unicast enable set regis

www.ti.comEthernet Media Access Controller (EMAC) Registers5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)The receive unicast clear register (RXU

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.24 Receive Maximum Length Register (RXMAXLEN)The receive maximum length register (RXMAXLE

www.ti.comEthernet Media Access Controller (EMAC) Registers5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)The receive fi

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)The receive channel 0-7

www.ti.comEthernet Media Access Controller (EMAC) Registers5.29 MAC Control Register (MACCONTROL)The MAC control register (MACCONTROL) is shown in Fig

www.ti.comRelated Documentation From Texas InstrumentsSPRUFH2 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Universal AsynchronousReceiver/Transm

Ethernet Media Access Controller (EMAC) Registerswww.ti.comTable 66. MAC Control Register (MACCONTROL) Field Descriptions (continued)Bit Field Value D

www.ti.comEthernet Media Access Controller (EMAC) Registers5.30 MAC Status Register (MACSTATUS)The MAC status register (MACSTATUS) is shown in Figure

Ethernet Media Access Controller (EMAC) Registerswww.ti.comTable 67. MAC Status Register (MACSTATUS) Field Descriptions (continued)Bit Field Value Des

www.ti.comEthernet Media Access Controller (EMAC) Registers5.31 Emulation Control Register (EMCONTROL)The emulation control register (EMCONTROL) is sh

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.33 MAC Configuration Register (MACCONFIG)The MAC configuration register (MACCONFIG) is sh

www.ti.comEthernet Media Access Controller (EMAC) Registers5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO)The MAC source address low bytes r

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.37 MAC Hash Address Register 1 (MACHASH1)The MAC hash registers allow group addressed fra

www.ti.comEthernet Media Access Controller (EMAC) Registers5.39 Back Off Test Register (BOFFTEST)The back off test register (BOFFTEST) is shown in Fig

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.41 Receive Pause Timer Register (RXPAUSE)The receive pause timer register (RXPAUSE) is sh

www.ti.comEthernet Media Access Controller (EMAC) Registers5.43 MAC Address Low Bytes Register (MACADDRLO)The MAC address low bytes register used in a

Related Documentation From Texas Instrumentswww.ti.comSPRUFI5 — TMS320DM36x Digital Media System-on-Chip (DMSoC) Ethernet Media AccessController (EMAC

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.44 MAC Address High Bytes Register (MACADDRHI)The MAC address high bytes register (MACADD

www.ti.comEthernet Media Access Controller (EMAC) Registers5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP)The transmit channel

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)The transmit channel 0-7 compl

www.ti.comEthernet Media Access Controller (EMAC) Registers5.50 Network Statistics RegistersThe EMAC has a set of statistics that record events associ

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES)The total number of IEEE 802.3X pause f

www.ti.comEthernet Media Access Controller (EMAC) Registers5.50.8 Receive Jabber Frames Register (RXJABBER)The total number of jabber frames received

Ethernet Media Access Controller (EMAC) Registerswww.ti.comThis may not be an exact count because the receive overruns statistic is independent of the

www.ti.comEthernet Media Access Controller (EMAC) Registers5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES)The total number of IEEE 802.3X pause

Ethernet Media Access Controller (EMAC) Registerswww.ti.comCRC errors have no effect on this statistic.5.50.22 Transmit Excessive Collision Frames Reg

www.ti.comEthernet Media Access Controller (EMAC) Registers• Was exactly 64-bytes long. (If the frame was being transmitted and experienced carrier lo

User's GuideSPRUFI5B–March 2009–Revised December 2010Ethernet Media Access Controller (EMAC)/ManagementData Input/Output (MDIO)1 IntroductionThis

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.50.33 Network Octet Frames Register (NETOCTETS)The total number of bytes of frame data re

www.ti.comAppendix A GlossaryBroadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernetdevices on the local network. The

Appendix Awww.ti.comMulticast MAC Address— A class of MAC address that sends a packet to potentially more than onerecipient. A group address is specif

www.ti.comAppendix B Revision HistoryTable 88 lists the changes made since the previous version of this document.Table 88. Document Revision HistoryRe

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

ConfigurationbusDMA memorytransfercontrollerPeripheralbusEMACcontrolmoduleEMACmodule MDIOmoduleMIIbusMDIObusEMAC/MDIOinterruptsARMinterruptc

www.ti.comArchitectureThe EMAC and MDIO interrupts are combined within the control module, so only the control moduleinterrupt needs to be monitored b

EMAC_TX_CLKEMAC_TXD(3-0)EMAC_TX_ENEMAC_COLEMAC_CRSEMAC_RX_CLKEMAC_RXD(3-0)EMAC_RX_DVMRXERMDCLKMDIOPhysicallayerdevice(PHY)SystemcoreTransformer2.5 MHz

www.ti.comArchitectureTable 1. EMAC and MDIO Signals for MII InterfaceSignal Type DescriptionEMAC_TX_CLK I Transmit clock (EMAC_TX_CLK). The transmit

Preamble SFD Destination Source Len Data7 1 6 6 2 46−1500 4FCSNumber of bytesLegend: SFD=Start Frame Delimeter; FCS=Frame Check Sequence (CRC)Architec

www.ti.comArchitecture2.5.2 Ethernet’s Multiple Access ProtocolNodes in an Ethernet Local Area Network are interconnected by a broadcast channel, as a

2SPRUFI5B–March 2009–Revised December 2010Submit Documentation Feedback© 2009–2010, Texas Instruments Incorporated

SOP | EOP 600 60pBufferpNextPacket A60 bytes0SOPFragment 1Packet B5121514pBufferpNext512 bytesEOP00−−−Packet BFragment 3500 bytes502pBuffer−−−500pNext

www.ti.comArchitecture2.6.2 Transmit and Receive Descriptor QueuesThe EMAC module processes descriptors in linked list chains as discussed in Section

Architecturewww.ti.com2.6.3 Transmit and Receive EMAC InterruptsThe EMAC processes descriptors in linked list chains as discussed in Section 2.6.1, us

www.ti.comArchitecture2.6.4 Transmit Buffer Descriptor FormatA transmit (TX) buffer descriptor (Figure 6) is a contiguous block of four 32-bit data wo

Architecturewww.ti.com2.6.4.1 Next Descriptor PointerThe next descriptor pointer points to the 32-bit word aligned memory address of the next buffer d

www.ti.comArchitecture2.6.4.7 End of Packet (EOP) FlagWhen set, this flag indicates that the descriptor points to a packet buffer that is last for a g

Architecturewww.ti.com2.6.5 Receive Buffer Descriptor FormatA receive (RX) buffer descriptor (Figure 7) is a contiguous block of four 32-bit data word

www.ti.comArchitectureExample 2. Receive Buffer Descriptor in C Structure Format/*// EMAC Descriptor//// The following is the format of a single buffe

Architecturewww.ti.com2.6.5.4 Buffer LengthThis 16-bit field is used for two purposes:• Before the descriptor is first placed on the receive queue by

www.ti.comArchitecture2.6.5.11 Pass CRC (PASSCRC) FlagThis flag is set by the EMAC in the SOP buffer descriptor if the received packet includes the 4-

Preface ... 101 Int

Arbiter andbus switchesCPUDMA Controllers8K bytedescriptormemoryConfigurationregistersInterruptcontrol andpacing logicEMAC interruptsMDIO interruptsCo

www.ti.comArchitecture2.7.3 Interrupt ControlThe EMAC control module combines multiple interrupt conditions generated by the EMAC and MDIOmodules into

Architecturewww.ti.com2.7.3.3 Receive Threshold Pulse InterruptThe EMAC control module receives the eight individual receive threshold interrupts orig

EMACcontrolmoduleControlregistersand logicPHYmonitoringPeripheralclockMDIOclockgeneratorUSERINTMDIOinterfacepollingPHYMDCLKMDIOLINKINTConfiguration bu

Architecturewww.ti.com2.8.1.3 Active PHY MonitoringOnce a PHY candidate has been selected for use, the MDIO module transparently monitors its link sta

www.ti.comArchitecture2.8.2.1 Initializing the MDIO ModuleThe following steps are performed by the application software or device driver to initialize

Architecturewww.ti.com2.8.2.4 Example of MDIO Register Access CodeThe MDIO module uses the MDIO user access register (USERACCESSn) to access the PHY c

Clock andreset logicReceiveDMA engineInterruptcontrollerTransmitDMA engineControlregistersConfiguration busEMACcontrolmoduleConfiguration busRAMStateF

Architecturewww.ti.com2.9.1.3 MAC ReceiverThe MAC receiver detects and processes incoming network frames, de-frames them, and puts them intothe receiv

www.ti.comArchitecture2.9.2 EMAC Module Operational OverviewAfter reset, initialization, and configuration, the application software running on the ho

www.ti.com4.1 MDIO Version Register (VERSION) ... 704.2 MDIO Control Reg

Architecturewww.ti.com2.10 Media Independent Interface (MII)The following sections discuss the operation of the Media Independent Interface (MII) in 1

www.ti.comArchitecture2.10.1.3.1 Collision-Based Receive Buffer Flow ControlCollision-based receive buffer flow control provides a means of preventing

Architecturewww.ti.com2.10.2 Data TransmissionThe EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to thetransm

www.ti.comArchitecture2.10.2.6 Transmit Flow ControlIncoming pause frames are acted upon, when enabled, to prevent the EMAC from transmitting any furt

Architecturewww.ti.com2.11 Packet Receive Operation2.11.1 Receive DMA Host ConfigurationTo configure the receive DMA for operation the host must:• Ini

www.ti.comArchitecture2.11.3 Receive Address MatchingThe receive address block can store up to 32 addresses to be filtered or matched. Before enabling

Architecturewww.ti.com2.11.5 Host Free Buffer TrackingThe host must track free buffers for each enabled channel (including unicast, multicast, broadca

www.ti.comArchitecture• If the frame length is 1522, there are 1518 bytes transferred to memory. The last byte is the last databyte.2.11.8 Promiscuous

Architecturewww.ti.comTable 4. Receive Frame Treatment Summary (continued)Address Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Receive Frame Treatment1 X 1 1

www.ti.comArchitecture2.12 Packet Transmit OperationThe transmit DMA is an eight channel interface. Priority between the eight queues may be either fi

www.ti.com5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ... 1155.36 MAC Source Address High Byt

Architecturewww.ti.comReceive overrun is prevented if the receive memory cell latency is less than the time required to transmit a64-byte cell on the

www.ti.comArchitecture2.15.2 Hardware Reset ConsiderationsWhen a hardware reset occurs, the EMAC peripheral has its register values reset and all the

Architecturewww.ti.comExample 4. EMAC Control Module Initialization CodeUint32 tmpval ;/* Disable all the EMAC/MDIO interrupts in the control module *

www.ti.comArchitecture2.16.3 MDIO Module InitializationThe MDIO module is used to initially configure and monitor one or more external PHY devices. Ot

Architecturewww.ti.com2.16.4 EMAC Module InitializationThe EMAC module is used to send and receive data packets over the network. This is done bymaint

EMACcoreMDIOcoreRXTHRESHOLDPEND(0..7)ReceivethresholdinterruptRXPEND(0..7)ReceiveinterruptTXPEND(0..7)TransmitinterruptSTATPENDHOSTPENDMDIO_USER

Architecturewww.ti.comEach of the eight transmit channel interrupts may be individually enabled by setting the correspondingbit in the transmit interr

www.ti.comArchitecture2.17.1.4 Statistics InterruptThe statistics level interrupt (STATPEND) is issued when any statistics value is greater than or eq

Architecturewww.ti.com2.17.2 MDIO Module Interrupt Events and RequestsThe MDIO module generates two interrupt events:• LINKINT: Serial interface link

www.ti.comArchitecture2.18 Power ManagementEach of the three main components of the EMAC peripheral can independently be placed inreduced-power modes

www.ti.comList of Figures1 EMAC and MDIO Block Diagram... 142 Eth

EMAC Control Module Registerswww.ti.com3 EMAC Control Module RegistersTable 7 lists the memory-mapped registers for the EMAC control module. See the d

www.ti.comEMAC Control Module Registers3.2 EMAC Control Module Software Reset Register (CMSOFTRESET)The software reset register (CMSOFTRESET) is shown

EMAC Control Module Registerswww.ti.com3.4 EMAC Control Module Interrupt Control Register (CMINTCTRL)The interrupt control register (CMINTCTRL) is sho

www.ti.comEMAC Control Module Registers3.5 EMAC Control Module Receive Threshold Interrupt Enable Register(CMRXTHRESHINTEN)The receive threshold inter

EMAC Control Module Registerswww.ti.com3.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)The transmit interrupt enable register (C

www.ti.comEMAC Control Module Registers3.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN)The miscellaneous interrupt enable

EMAC Control Module Registerswww.ti.com3.9 EMAC Control Module Receive Threshold Interrupt Status Register(CMRXTHRESHINTSTAT)The receive threshold int

www.ti.comEMAC Control Module Registers3.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT)The transmit interrupt status register

EMAC Control Module Registerswww.ti.com3.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT)The miscellaneous interrupt status

www.ti.comEMAC Control Module Registers3.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX)The receive interrupts per mil

www.ti.com48 Transmit Interrupt Mask Set Register (TXINTMASKSET) ... 9249 Transmit Interrupt M

MDIO Registerswww.ti.com4 MDIO RegistersTable 22 lists the memory-mapped registers for the MDIO module. See the device-specific data manualfor the mem

www.ti.comMDIO Registers4.2 MDIO Control Register (CONTROL)The MDIO control register (CONTROL) is shown in Figure 27 and described in Table 24.Figure

MDIO Registerswww.ti.com4.3 PHY Acknowledge Status Register (ALIVE)The PHY acknowledge status register (ALIVE) is shown in Figure 28 and described in

www.ti.comMDIO Registers4.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)The MDIO link status change interrupt (unmasked) registe

MDIO Registerswww.ti.com4.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)The MDIO link status change interrupt (masked) register

www.ti.comMDIO Registers4.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)The MDIO user command complete interrupt (unmasked) r

MDIO Registerswww.ti.com4.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)The MDIO user command complete interrupt (masked) re

www.ti.comMDIO Registers4.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)The MDIO user command complete interrupt mask set r

MDIO Registerswww.ti.com4.10 MDIO User Command Complete Interrupt Mask Clear Register(USERINTMASKCLEAR)The MDIO user command complete interrupt mask c

www.ti.comMDIO Registers4.11 MDIO User Access Register 0 (USERACCESS0)The MDIO user access register 0 (USERACCESS0) is shown in Figure 36 and describe

www.ti.comList of Tables1 EMAC and MDIO Signals for MII Interface... 172 Eth

MDIO Registerswww.ti.com4.12 MDIO User PHY Select Register 0 (USERPHYSEL0)The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 37 and

www.ti.comMDIO Registers4.13 MDIO User Access Register 1 (USERACCESS1)The MDIO user access register 1 (USERACCESS1) is shown in Figure 38 and describe

MDIO Registerswww.ti.com4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 39 and

www.ti.comEthernet Media Access Controller (EMAC) Registers5 Ethernet Media Access Controller (EMAC) RegistersTable 37 lists the memory-mapped registe

Ethernet Media Access Controller (EMAC) Registerswww.ti.comTable 37. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Regis

www.ti.comEthernet Media Access Controller (EMAC) RegistersTable 37. Ethernet Media Access Controller (EMAC) Registers (continued)Offset Acronym Regis

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.1 Transmit Identification and Version Register (TXIDVER)The transmit identification and v

www.ti.comEthernet Media Access Controller (EMAC) Registers5.3 Transmit Teardown Register (TXTEARDOWN)The transmit teardown register (TXTEARDOWN) is s

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.4 Receive Identification and Version Register (RXIDVER)The receive identification and ver

www.ti.comEthernet Media Access Controller (EMAC) Registers5.5 Receive Control Register (RXCONTROL)The receive control register (RXCONTROL) is shown i

www.ti.com46 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ... 9247 Transmit Interrupt Mask

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)The transmit interrupt stat

www.ti.comEthernet Media Access Controller (EMAC) Registers5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)The transmit interrupt sta

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET)The transmit interrupt mask set regi

www.ti.comEthernet Media Access Controller (EMAC) Registers5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)The transmit interrupt mask cle

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.11 MAC Input Vector Register (MACINVECTOR)The MAC input vector register (MACINVECTOR) is

www.ti.comEthernet Media Access Controller (EMAC) Registers5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)The receive interrupt statu

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)The receive interrupt stat

www.ti.comEthernet Media Access Controller (EMAC) Registers5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)The receive interrupt mask set regis

Ethernet Media Access Controller (EMAC) Registerswww.ti.com5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)The receive interrupt mask clear

www.ti.comEthernet Media Access Controller (EMAC) Registers5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)The MAC interrupt status (unma