Texas-instruments TMS320DM646X DMSOC Instrukcja Użytkownika Strona 1

TMS320DM646x DMSoCAsynchronous External Memory Interface(EMIF)User's GuideLiterature Number: SPRUEQ7CFebruary 2010

Architecturewww.ti.com2.3 Signal DescriptionsTable 1 describes the function of each of the EMIF pins.Table 1. EMIF PinsPins(s) I/O DescriptionEM_ A[22

EM_CS[5:2]EM_WEEM_OEEM_RWEM_WAIT[5:2]EM_BA[1:0]EM_D[15:0]EM_A[22:0]EMIFEM_D[7:0]EM_A[21:0]EM_BA[1:0]DQ[7:0]A[23:2]A[1:0]EMIF 8−bitasynchronousmemorya)

Architecturewww.ti.com2.5.2 Programmable Asynchronous ParametersThe EMIF allows a high degree of programmability for shaping asynchronous accesses. Th

www.ti.comArchitectureTable 3. Description of the Asynchronous Configuration Register (ACFGn) (continued)Parameter DescriptionASIZE Asynchronous Devic

Architecturewww.ti.com2.5.4 Read and Write Operations in Normal ModeNormal mode is the asynchronous interface's default mode of operation. The No

Internal clockEM_CS[5:2]EM_A/EM_BAEM_DEM_OEEM_WEEM_RWSetupStrobeHold232AddressDatawww.ti.comArchitectureFigure 4. Timing Waveform of an Asynchronous R

Architecturewww.ti.com2.5.4.2 Asynchronous Write Operations (Normal Mode)An asynchronous write is performed when any of the requesters mentioned in Se

Internal clockEM_CS[5:2]EM_A/EM_BAEM_DEM_OEEM_WEEM_RWSetupStrobeHold232AddressDatawww.ti.comArchitectureFigure 5. Timing Waveform of an Asynchronous W

Architecturewww.ti.com2.5.5 Read and Write Operations in Select Strobe ModeSelect Strobe mode is the EMIF's second mode of operation. The SS mode

Internal clockEM_CS[5:2]EM_A/EM_BAEM_DEM_OEEM_WEEM_RWSetupStrobeHold232AddressDatawww.ti.comArchitectureFigure 6. Timing Waveform of an Asynchronous R

2SPRUEQ7C–February 2010Submit Documentation FeedbackCopyright © 2010, Texas Instruments Incorporated

Architecturewww.ti.com2.5.5.2 Asynchronous Write Operations (Select Strobe Mode)An asynchronous write is performed when any of the requesters mentione

Internal clockEM_CS[5:2]EM_A/EM_BAEM_DEM_OEEM_WEEM_RWSetupStrobeHold232AddressDatawww.ti.comArchitectureFigure 7. Timing Waveform of an Asynchronous W

Architecturewww.ti.com2.5.6 NAND Flash ModeNAND Flash mode is the EMIF's third mode of operation. Each chip select space may be placed in NANDFla

CLE_EM_A[16]ALE_EM_A[17]EM_CS[n]EM_WEEM_OEEM_D[7:0]EM_WAIT[n]EMIFCLEALECEWEOEIO[7:0]R/BNAND flasha) Connection to 8-bit NAND deviceb) Connection to 16

Architecturewww.ti.com2.5.6.4 NAND Read and Program OperationsA NAND Flash access cycle is composed of a command, address, and data phase. The EMIF wi

Bit 7Bit 7Bit 7Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Bit 6Bit 5 Bit 4 Bit 2Bit 3 Bit 1 Bit 0Bit 6Bit 6Bit 1Bit 3 Bit 2Bit 4Bit 5Bit 5 Bit 4 Bi

EM_D[15:0]EM_RWEM_A[1:0]EM_WAITEM_OEEM_WEEM_CSEM_BA1GPIOxAEMIFHD[15:0]HR/WHCNTL[1:0]HRDYHDS1HCSHHWILHINTHDS2HASHPIENAHBEDAHBE1AHPI16VCCVCCVSSVSSArchit

www.ti.comArchitecture2.5.8 Extended Wait Mode and the EM_WAIT PinThe Extended Wait mode is a mode in which the external asynchronous device may asser

Architecturewww.ti.com2.5.11 Interrupt SupportThe EMIF has a single interrupt source (Table 13) mapped to the ARM interrupt controller. For moreinform

www.ti.comArchitecture2.5.11.2 Interrupt MultiplexingThe EMIF interrupt is supported by both the ARM and DSP. The interrupt is not multiplexed with an

Preface ... 61 Int

EM_CSEM_WEEM_OEA[18:0]EM_BA[1]EM_D[15:0]CEWEOELBUBA[19:1]A[0]DQ[15:0]VS SVSSEMIF TC5516100FT−12Use Caseswww.ti.com3 Use CasesThe EMIF allows a high de

R_SETUP ) R_STROBE wǒtACC(m) ) tSUǓtcyc* 1R_SETUP ) R_STROBE ) R_HOLD wtRC(m)tcyc* 3R_HOLD wǒtH* tOH(m)Ǔtcyc* 1TA wtCOD(m)tcyc* 1www.ti.comUse Cases3.

tRC(m)StrobeSetup HoldEM_CSEM_A[21:0]EM_BA[1:0]EM_OEEM_D[15:0]tACC(m)tSUtHtCOD(m)tOH(m)Use Caseswww.ti.comFigure 12. Timing Waveform of an ASRAM ReadF

W_STROBE wtWP(m)tcyc* 1W_SETUP ) W_STROBE w maxǒtAW(m)tcyc,tDS(m)tcycǓ* 1W_HOLD w maxǒtWR(m)tcyc,tDH(m)tcycǓ* 1W_SETUP ) W_STROBE ) W_HOLD wtWC(m)tcyc

R_SETUP ) R_STROBE wǒtEM_A) tACC(m) ) tSU) tEM_DǓtcyc* 1R_SETUP ) R_STROBE ) R_HOLD wtRC(m)tcyc* 3R_HOLD wǒtH* tEM_D* tOH(m) * tEM_AǓtcyc* 1TA wǒtEM_C

1Setup2Strobe3Hold4EM_CSEM_CS (ASRAM)EM_A[21:0]/EM_BA[1:0]EM_A[21:0]/EM_BA[1:0] (ASRAM)EM_OEEM_OE (ASRAM)EM_D[15:0]EM_D[15:0](ASRAM)tCStCStRC(m)tEM_At

W_STROBE wtWP(m)tcyc* 1W_SETUP ) W_STROBE w maxǒǒtEM_A) tAW(m) * tEM_WEǓtcyc,ǒtEM_D) tDS(m) * tEM_WEǓtcycǓ* 1W_HOLD w maxǒǒtEM_WE) tWR(m) * tEM_AǓtcyc

www.ti.comUse Cases3.1.4 Example Using TC5516100FT-12This section takes you through the configuration steps required to implement Toshiba’s TC55V1664F

R_SETUP ) R_STROBE wǒtEM_A) tACC(m) ) tSU) tEM_DǓtcyc* 1 w(0.27 ) 12 ) 5 ) 0.45)10* 1 w 0.78R_SETUP ) R_STROBE ) R_HOLD wtRC(m)tcyc* 3 wǒ1210Ǔ* 3 w *

www.ti.comUse CasesSince the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fieldsare equal to EMIF clock cycles minus 1 cycle

www.ti.comList of Figures1 EMIF Functional Block Diagram ... 92

Use Caseswww.ti.com3.2.2 Meeting AC Timing Requirements for NAND FlashWhen configuring the EMIF to interface to NAND Flash, you must consider the AC t

R_SETUP wtCLR(m)tcyc* 1R_STROBE w maxǒǒtREA(m) ) tSUǓtcyc,tRP(m)tcycǓ* 1R_SETUP ) R_STROBE wǒtCEA(m) ) tSUǓtcyc* 1R_HOLD wǒtH* tCHZ(m)Ǔtcyc* 1R_SETUP

W_SETUP w maxǒtCLS(m)tcyc,tALS(m)tcyc,tCS(m)tcycǓ* 1W_STROBE wtWP(m)tcyc* 1W_SETUP ) W_STROBE wtDS(m)tcyc* 1W_HOLD w maxǒtCLH(m)tcyc,tALH(m)tcyc,tCH(m

tCH(m)tWC(m)tALH(m)tCLH(m)tWP(m)EM_CSALE_EM_A[1]CLE_EM_A[2]EM_WEEM_D[7:0]tCS(m)tALS(m)tCLS(m)tDS(m)tDH(m)SetupStrobeHoldtCH(m)tWC(m)tALH(m)tCLH(m)tWP(

tCH(m)tWC(m)tALH(m)tCLH(m)tWP(m)EM_CSALE_EM_A[1]CLE_EM_A[2]EM_WEEM_D[7:0]tCS(m)tALS(m)tCLS(m)tDS(m)tDH(m)SetupStrobeHoldUse Caseswww.ti.comFigure 19.

www.ti.comUse Cases3.2.3 Example Using Hynix HY27UA081G1MThis section takes you through the configuration steps required to implement Hynix’s HY27UA08

R_SETUP wtCLR(m)tcyc* 1 wǒ1010Ǔ* 1 w 0R_STROBE w maxǒǒtREA(m) ) tSUǓtcyc,tRPtcycǓ* 1 wǒ6510Ǔ* 1 w 5.5R_SETUP ) R_STROBE wǒtCEA) tSUǓtcyc* 1 w(75 ) 5)1

www.ti.comUse CasesSince the value of the W_SETUP/R_SETUP, W_STROBE/R_STROBE, W_HOLD/R_HOLD, and TA fieldsare equal to EMIF clock cycles minus 1 cycle

Registerswww.ti.com4 RegistersThe external memory interface (EMIF) is controlled by programming its internal memory-mapped registers(MMRs). Table 32 l

www.ti.comRegisters4.1 Revision Code and Status Register (RCSR)The revision code and status register (RCSR) is shown in Figure 20 and described in Tab

www.ti.comList of Tables1 EMIF Pins ...

Registerswww.ti.com4.2 Asynchronous Wait Cycle Configuration Register (AWCCR)The asynchronous wait cycle configuration register (AWCCR) is used to con

www.ti.comRegistersTable 34. Asynchronous Wait Cycle Configuration Register (AWCCR) Field Descriptions (continued)Bit Field Value Description17-16 CS2

Registerswww.ti.com4.3 Asynchronous n Configuration Registers (A1CR-A4CR)The asynchronous configuration register (ACFGn) is used to configure the shap

www.ti.comRegisters4.4 EMIF Interrupt Raw Register (EIRR)The EMIF interrupt raw register (EIRR) is used to monitor and clear the EMIF’s hardware-gener

Registerswww.ti.com4.5 EMIF Interrupt Mask Register (EIMR)Similar to the EMIF interrupt raw register (EIRR), the EMIF interrupt mask register (EIMR) i

www.ti.comRegistersTable 37. EMIF Interrupt Mask Register (EIMR) Field Descriptions (continued)Bit Field Value Description0 ATM Asynchronous Timeout M

Registerswww.ti.com4.6 EMIF Interrupt Mask Set Register (EIMSR)The EMIF interrupt mask set register (EIMSR) is used to enable the interrupts. If a bit

www.ti.comRegistersTable 38. EMIF Interrupt Mask Set Register (EIMSR) Field Descriptions (continued)Bit Field Value Description0 ATMSET Asynchronous T

Registerswww.ti.com4.7 EMIF Interrupt Mask Clear Register (EIMCR)The EMIF interrupt mask clear register (EIMCR) is used to disable the interrupts. If

www.ti.comRegistersTable 39. EMIF Interrupt Mask Clear Register (EIMCR) Field Descriptions (continued)Bit Field Value Description0 ATMCLR Asynchronous

PrefaceSPRUEQ7C–February 2010Read This FirstAbout This ManualThis document describes the asynchronous external memory interface (EMIF) in the TMS320DM

Registerswww.ti.com4.8 NAND Flash Control Register (NANDFCR)The NAND Flash control register (NANDFCR) is shown in Figure 27 and described in Table 40.

www.ti.comRegisters4.9 NAND Flash Status Register (NANDFSR)The NAND Flash status register (NANDFSR) is shown in Figure 28 and described in Table 41.Fi

Registerswww.ti.comFigure 29. NAND Flash n ECC Register (NANDECCn)31 28 27 26 25 24Reserved P2048O P1024O P512O P256OR-0 R-0 R-0 R-0 R-023 22 21 20 19

www.ti.comAppendix A Revision HistoryTable 43 lists the changes made since the previous version of this document.Table 43. Document Revision HistoryRe

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

www.ti.comRelated Documentation From Texas InstrumentsSPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digitalsignal pr

User's GuideSPRUEQ7C–February 2010Asynchronous External Memory Interface (EMIF)1 IntroductionThis document describes the operation of the asynchr

EM_CS[5:2]EM_OEEM_RWEM_WAIT[5:2]EM_WEEM_BA[1:0]EM_D[15:0]EM_A[22:0]EMIFSCRVICPDSPARMEDMA3Master peripheralswww.ti.comArchitecture1.3 Functional Block