Texas-instruments TMS320TCI6486 Instrukcja Użytkownika Strona 110
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EMAC Port Registers
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5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 58 and described in
Table 52.
Figure 58. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
31 24
Reserved
R-0
23 22 21 20 19 18 17 16
RX7PULSE RX6PULSE RX5PULSE RX4PULSE RX3PULSE RX2PULSE RX1PULSE RX0PULSE
MASK MASK MASK MASK MASK MASK MASK MASK
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
RX7PEND RX6PEND RX5PEND RX4PEND RX3PEND RX2PEND RX1PEND RX0PEND
MASK MASK MASK MASK MASK MASK MASK MASK
LEGEND: R = Read only; R/W = Read/Write; R/WC = Read/Write 1 to clear; -n = value after reset
Table 52. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
Bit Field Value Description
31-24 Reserved 0 Reserved; read as 0.
23 RX7PULSEMASK 0 Receive channel 7 pulse interrupt mask. Write 1 to disable interrupt.
22 RX6PULSEMASK 0 Receive channel 6 pulse interrupt mask. Write 1 to disable interrupt.
21 RX5PULSEMASK 0 Receive channel 5 pulse interrupt mask. Write 1 to disable interrupt.
20 RX4PULSEMASK 0 Receive channel 4 pulse interrupt mask. Write 1 to disable interrupt.
19 RX3PULSEMASK 0 Receive channel 3 pulse interrupt mask. Write 1 to disable interrupt.
18 RX2PULSEMASK 0 Receive channel 2 pulse interrupt mask. Write 1 to disable interrupt.
17 RX1PULSEMASK 0 Receive channel 1 pulse interrupt mask. Write 1 to disable interrupt.
16 RX0PULSEMASK 0 Receive channel 0 pulse interrupt mask. Write 1 to disable interrupt.
15-8 Reserved 0 Reserved; read as 0.
7 RX7PENDMASK 0 Receive channel 7 pending interrupt mask. Write 1 to disable interrupt.
6 RX6PENDMASK 0 Receive channel 6 pending interrupt mask. Write 1 to disable interrupt.
5 RX5PENDMASK 0 Receive channel 5 pending interrupt mask. Write 1 to disable interrupt.
4 RX4PENDMASK 0 Receive channel 4 pending interrupt mask. Write 1 to disable interrupt.
3 RX3PENDMASK 0 Receive channel 3 pending interrupt mask. Write 1 to disable interrupt.
2 RX2PENDMASK 0 Receive channel 2 pending interrupt mask. Write 1 to disable interrupt.
1 RX1PENDMASK 0 Receive channel 1 pending interrupt mask. Write 1 to disable interrupt.
0 RX0PENDMASK 0 Receive channel 0 pending interrupt mask. Write 1 to disable interrupt.
110
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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Copyright © 2006–2010, Texas Instruments Incorporated
- User's Guide 1
- Submit Documentation Feedback 2
- Read This First 10
- C6472/TCI6486 EMAC/MDIO 11
- 1.3 Functional Block Diagram 12
- Introduction 13
- 2.1 Clock Control 15
- 2.2 Memory Map 16
- 2.3 System-Level Connections 17
- EMAC Functional Architecture 18
- 2.5 Programming Interface 31
- PS_TICK=1&& 43
- TIME>= TIME_CFG 43
- 2.9 EMAC Module 52
- 2.11 Packet Receive Operation 58
- 2.14 Transfer Node Priority 63
- 2.15 Reset Considerations 64
- 2.16 Initialization 65
- 2.17 Interrupt Support 67
- 2.18 Power Management 69
- 2.19 Emulation Considerations 69
- 3 EMIC Module Registers 71
- 3.1 EW_INTCTL Registers 71
- 3.2 RPIC Registers 71
- Figure 24. RPCFG Register 72
- EMIC Module Registers 73
- 3.3 TPIC Registers 74
- 4 MDIO Registers 76
- 4.1 Introduction 76
- MDIO Registers 77
- (USERINTMASKCLEAR) 86
- 5 EMAC Port Registers 91
- Table 37 95
- Table 40 98
- EMAC Port Registers 100
- Table 45 103
- Table 46 104
- Table 48 106
- Table 51 109
- Table 52 110
- Table 55 113
- Table 56 114
- (RXMBPENABLE) 115
- Descriptions (continued) 116
- Table 58 118
- Descriptions 122
- 23 19 18 17 16 125
- R-0 R/W-0 R/W-0 R/W-0 125
- 15 14 13 12 11 10 9 8 125
- Table 71 133
- Table 72 134
- Table 76 138
- Table 84 146
- Table 85 147
- Appendix A Glossary 157
- Appendix A 158
- Appendix B Revision History 159
- IMPORTANT NOTICE 160
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