Texas Instruments TMS320C6202 Instrukcja Użytkownika Pobierz pdf (Strona 46)

TMS320C6202

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS072B – AUGUST 1998 – REVISED AUGUST 1999

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)

XA1 XA2 XA3 XA4

D1 D2 D3 D4

XFCLK

XCEx

XBE[3:0]/XA[5:2]

†

XOE

XRE

XWE/XWAIT

‡

XD[31:0]

†

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

‡

XWE

/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Figure 27. FIFO Read Timing

XA1 XA2 XA3 XA4

D1 D2 D3 D4

XFCLK

XCEx

XBE[3:0]/XA[5:2]

†

XOE

XRE

XD[31:0]

XWE/XWAIT

‡

†

XBE[3:0]

/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

‡

XWE

/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Figure 28. FIFO Write Timing

ADVANCE INFORMATION

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 73 74

Brak uwag

Texas Instruments TMS320C6202 Instrukcja Użytkownika Strona 46